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Msg  16248 of 18794  at  10/1/2010 10:29:20 PM  by


Appl new standard, called PPN (Perfect Page New)

 From Shlomi Cohen this morning

"What is worth noting is that NAND pricing is that the price gap for the same density, based

on different process technology node as well as type (either 2 bit per cell multi-level cell

MLC or 3 bit per cell TLC) remains quite large in 2010, especially in 3Q10. The gap goes

up to as high as 3x for 32Gb NAND. We attribute the pricing weakness to the low quality of

TLC chips, which are sold at discount to the spot market, especially when Samsung

increased TLC production from 0% to 20% of output mix during the year. While TLC has

had no price premium relative to cost advantage, we expect that there will be no further

headwinds to TLC pricing.

In addition, delay in 20nm production from key customer Apple has increased pricing

pressure. The delay is due to Apple’s new standard, called PPN (Perfect Page New) for

NAND flash to extend the cycle time by as many as 3 times vs. 30nm NAND flash

currently in use. For example, current chips are guaranteed for up to 1,000 program/ erase

cycles for 1 year; while the Apple standard (exclusive to Apple for now) requires 3,000

cycles over 3 years. However, for the new standard, better controller technology to detect

and manipulate “about to fail” bits is required. We expect the successful qualification of

20nm process will result in wider adoption into a variety of new embedded applications, i.e.

smartphones, which would be a good catalyst for price stabilization."

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