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Msg  794160 of 794296  at  9/24/2021 2:15:50 PM  by

twobytebus


DDR5 Duty Cycle Adjustments

Micron on page 5 of 6 for DCA:

<<Enables the controller to compensate for duty cycle distortion (DCD) on all DQS and DQ pins by adjusting the duty cycle inside the DRAM. >>
 
 
And here's Rambus' patent - it looks to be good until 2031:
 
United States Patent9,824,730
Giovannini , et al.November 21, 2017

Memory components and controllers that calibrate multiphase synchronous timing references

Abstract

A first timing reference signal and a second timing reference signal are sent to a memory device. The second timing reference signal has approximately a quadrature phase relationship with respect to the first timing reference signal. A plurality of serial data patterns are received from the memory device. The transitions of the first timing reference and the second timing reference determining when transitions occur between the bits of the plurality of data patterns. Timing indicators associated with when received transitions occur between the bits of the plurality of data patterns are received from the memory device. The timing indicators are each measured using a single sampler. Based on the timing indicators, a first duty cycle adjustment for the first timing reference signal, a second duty cycle adjustment for the second timing reference signal, and a quadrature phase adjustment are determined and applied.



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