|
|
|
|
||
Anatomy of a 112-Gbps ADC/DSP Long-Reach SerDes PHYTuesday, March 12, 2019 - By Kenneth Dyer Higher data rates for next-generation data centers require changes in SerDes PHY technologies, so PAM-4 is stepping in to replace the long-standing NRZ encoding scheme It’s been said that SerDes physical layers (PHYs) aren’t created equal. The most acceptable PHY is the one with the right mix of features required for the targeted data center, high-performance computing (HPC), networking, and enterprise applications. Today, systems-on-chip (SoC) and system designers are closely eyeing those applications and looking to increase channel data rates. The 112-gigabit-per-second (Gbps) analog-to-digital converter (ADC)-based long-reach (LR) SerDes PHY is the top contender to boost greater performance with acceptable power and area. Take Rambus’s version, for example (Figure 1), showing both transmit (serializer) and receive (deserializer) sections. Initially described here is analog circuitry. As shown in the block diagram, the transceiver lane comprises a serializer that formats transmitted data to be sent over the line, a symbol encoder that picks up logic 1s and logic 0s or PAM-4 data, and a buffer that reliably drives things out. Figure 1: Conventional ADC + DSP LR transceiver architecture (Source: Rambus) As seen on the lower-right-hand side of the block diagram, the receiver, or deserializer, has electrostatic discharge (ESD) protection, which is highly important to deal with these high-frequency inputs. ESD protection is critical because as frequency increases, circuits become more delicate. Therefore, robust ESD circuitry is required to avoid failures. The receiver comprises an input termination network along with a continuous linear time equalizer (CTLE) and programmable gain amplifier (PGA). This drives the ADC. The remaining circuitry is all digital signal processing (DSP). Following the ADC is a feed-forward equalizer (FFE) digital block. This is like a digital high-pass filter that is tuned to match line characteristics. Tuning is performed electronically. Signal condition and FFE output are reviewed and adapted to achieve the best response over a wide range of channels. Following the FFE is the decision feedback equalizer (DFE), which is also a high-pass filter. The difference between the FFE and the DFE is that, as its name implies, the DFE makes a decision regarding the symbol (one of several voltages) received. The output of this digital equalizer (EQ) drives the clock and data recovery circuit (CDR) and automatic gain control. Data from the output of this DSP circuitry then passes to the receiver (RX) interface, which drives data out of the PHY. In some applications, the SoC or system designer may want data in different ways. They may also opt to have a forward error correction (FEC) on the output of the receiver to improve the bit error rate (BER) of the received data. FEC performs this operation by using redundancy. It transmits slightly faster than the data required; hence, extra information is transmitted. By reviewing the extra information in the received signal, the FEC determines if mistakes have occurred or not. PAM-4 makes it happen To understand the reasoning behind this, we first need to look at Nyquist loss for NRZ data for a generic legacy channel and for 112-Gbps data transmission (Figure 2). Nyquist loss is the insertion loss of the input signal at half the symbol rate. For NRZ at 112 Gbps, this is nominally 56 GHz. NRZ involves two-level data and, as shown in the chart, it’s at a really low 70 dB at 56 GHz. The red line indicating crosstalk is considerably above the blue trace, which shows signal loss. Figure 2: Nyquist loss for NRZ data for a generic legacy channel and 112-Gbps data transmission (Source: Rambus) In short, crosstalk has more power than the signal; hence, the signal-to-noise ratio (SNR) is negative, which means error-free communication or signal recovery is not possible. In this case, if a transmitter is operated at 56 Gbps, data would not be received at all. Therefore, PAM-4 becomes a more viable solution. The Nyquist rate for 112 Gbps using PAM-4 is 28 GHz. In comparison to NRZ with its two voltage levels at logic 0 and logic 1, PAM-4 uses four voltage levels to represent four combinations of two bits: 11, 10, 01, and 00 (Figure 3a). Figure 3a: NRZ/PAM-2 uses two voltage levels to represent logic 0 and logic 1. PAM-4 uses four voltage levels to represent four combinations of two bits of logic: 11, 10, 01, and 00. (Source: Tektronix) Using PAM-4, the transmit frequency is shown in the orange part of the right-hand bar in Figure 3b. Transmitting two bits per symbol using PAM-4, the Nyquist is at 28 GHz. In this case, the blue trace in Figure 2 has a signal loss of about 35 dB, and crosstalk is about 20 dB below that. Here, the SNR is positive, meaning error-free information can be transmitted over this channel. Figure 3b: Transmit frequency is shown in the orange part of the right-hand bar. (Source: Rambus) As illustrated here, 112 Gbps can be performed only by using PAM-4. Conversely, by using NRZ, crosstalk and signal loss are combined in such a manner that the signal cannot be received. Also, PAM-4’s four voltage levels allow signal transmission at those four levels. Instead of NRZ’s one large transmit eye, PAM-4 provides three eye diagrams (Figure 3b). By going to PAM-4, there is a 9-dB signal loss. While PAM-4 reduces crosstalk, three smaller eyes are transmitted. However, combined, they have the same peak-to-peak transmit amplitude as an NRZ eye. Instead of one large eye diagram with NRZ, there are three of them with PAM-4, and so then, a loss of SNR is the result. This calls for using DSP, which enables complex modulation schemes like PAM-4. Taking another look at the transceiver Figure 4: Conventional PAM-4 transceiver with ADC-based receiver (Source: Rambus) There are ESD networks at both transmitter and receiver, as well as a termination network. Input signals are finally received on the resistive termination network. The termination resistor output is a capacitor coupled to a CTLE, which provides a high-frequency boost to the input. The CTLE performs the first stage of high pass to equalize the channel and compensate for the low pass. That’s important because it’s noise. It’s difficult to eliminate or reduce the CTLE because when the ADC operates, it adds noise to the output. This is called quantization noise; the ADC quantizes the input, and the resulting quantization noise is wide-band. If a DSP-based high-pass equalizer is placed after the ADC, it will boost the quantization noise; hence, a trade-off is necessary in this instance. If there isn’t a CTLE, at least two more bits would be required on the ADC. Two more bits are too much; a 6-bit ADC would have up to 8 bits, and the cost of increasing ADC that much dwarfs the cost of the CTLE. From a cost/performance point of view, more CTLE is required, and what this does is shrink the ADC area and power. The output from the ADC is serial to parallel working at 56 giga-samples per second (GS/s). The data is aligned to an 875-MHz clock and then goes into the DSP block, which has an FFE in the EQ block and a DFE in the feedback box. The output is digital data that matches the data coming in. This also controls time recovery. The DSP output also goes to a phase rotator, shown by a circle with an arrow in it, whose job is to tune the sampling phase of the ADC to be in the middle of the eye. How DSP plays its role Also, the CTLE has traditionally been a highly sensitive analog circuit. On the other hand, DSP is digital with extra adders, accumulators, and multipliers. Hence, the DSP is easier to design. Because of this, there is no design concern about analog noise, distortion, and all the other impairments associated with analog circuits. This way, for example, the complexity of an equalizer can be increased simply by growing it digitally, wherein power scales linearly, versus performing it in a CTLE, which scales geometrically. Digital design is portable, robust, repeatable, and predictable. In this context, “portable” refers to potentially having different PHY versions or a receiver with different DSPs. The ADC can be a major challenge, but it is optimized here with the benefits of the DSP. Conclusion |
return to message board, top of board |