<<DDR5 memory modules will keep using DDR4’s 288-pin arrangement, but because next-gen DDR5 DIMMs will have two separate 32-bit I/O channels, there will be a number of differences when it comes to overall module architecture.>>
Here's Rambus:
<<Module ThreadingThe growing trend of multi-core processing and converged graphics-compute processors is increasing the performance requirements on the DRAM memory subsystems. Multi-thread computing and graphics not only need higher memory bandwidth but also generate more random accesses to smaller pieces of data. Module Threading improves the throughput and power efficiency of a memory module by applying parallelism to module data accesses. This innovation partitions the module into two individual memory channels and interleaves the commands to each respective channel. The result is a smaller minimum transfer size and reduced row activation power, translating to 50% higher bandwidth and 20% lower memory power compared to a conventional DIMM module. - Improves memory throughput up to 50%
- Reduces power consumption by 20% for equivalent workloads versus conventional modules
- Enables full utilization of memory IO bandwidth
- Utilizes conventional DRAM
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