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Msg  560174 of 789174  at  11/8/2010 3:23:40 PM  by

sabatino


Steven Woo asked about the future of XDR

Japanese to English translation

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http://pc.watch.impress.co.jp/docs/news/20101109_405569.html

◇ ◇ Recent Posts 
[November 9] 
Rambus Reports ■ Press Conference 
~ Steven Woo asked about the future of XDR Dr. 
 
Rambus Reports Press Conference 
~ Steven Woo asked about the future of XDR Dr. 

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Rambus Inc., Ramubasudezainsemina 10 in 26 in Osaka and Osaka were held to hold a press conference in Tokyo ahead of this, we introduce some of the content prior to the session. Also, since I talk to over Moteta opportunities and one-on-one according to which speakers, along what I want to introduce (Photo 1). 

● Press Conference Summary 
The press conference was its first Director of the Linda Ashmore outlined his company can easily last (Figure 2). Even though, so no new information. Major events (Fig. 3) and related trends Lighting (4 photo) was about a little new. 


[Photo 1] Although he left Linda Ashmore Rambus Headquarters (Director, Corporate Communications), Dr. Steven Woo as the right (Technical Director) [2] This is the main photo and graphics for mobile, in that second half display-related The pass was a bold 

[Photo] 3 months and 8 NVIDIA's patent licensing here. However, "some still on the license only" (Ashmore said) and that they could not increase the license agreement will further reports [4] Fukuda photos are included 居Nakatta last year on Mon 12 Rambus has GLT (Global Lighting Technologies), and to obtain patents and related technology light from, but were or are on display at a seminar last a waveguide based on this, the sales even in this regard immediately 5 photos will be standing for the first time since 2007 Woo - When I met Dr. TBI (Terabyte Initiative) was the title of Architect, and that has recently dominated the overall business 
Following is the Technical Director Dr. Steven Woo (5 photos), the "challenge and response for next generation mobile memory and graphics memory," the theme of the session were held. In fact, a big change from the content itself is not a report of Fukuda. If the aperture point 

· XDR2 16Gbps/pin maximum transfer rate could be demonstrated. Therefore, there is a traditional and consumer products for the time being XDR2 XDR DRAM market was not the coverage, GDDR5 aim to replace 
· XDR Mobile for mobile devices, we aim to adopt aggressive 

That it became, was carried out in line with this description. As a basic concept is becoming increasingly difficult in that meet all three demands of the performance-cost power (Photo 6) showed that the approach should become necessary to co-design (picture 7.) 


Well this story photo [6] [7 photos] general design only and not in the form or design of circuits and signal integrity, about the need to proceed at once while watching the entire design 
The agenda here is the fact that is becoming difficult to improve the speed of the memory per pin using the conventional short (Photo 8). Unfortunately, the design of signal transmission as well as simply becoming harder to measure verification and debugging (Photo 9). Mean that slowing down is not allowed for improved performance (10 pictures). 


[8] With the picture performance, but the bandwidth required is increasing, work together to increase the bus width is impossible because the only way to speed up the signal no matter what. Increasing the speed signal, however, susceptible to noise and really, the more power. For that matter, must contain a mechanism for speeding up to a 9 - Pictures and the stub can pick the probe that, QFP packages such as BGA Apart from the direct probe will hit is impossible [10] This is a picture from the slide back. GPU might be most apparent cases of lack of bandwidth 
One of the company's solution to this problem is not that XDR2 (11 photos). XDR2 itself from the initially positioned as high-speed version of the XDR, XDR + TDI was captured and turned into a variety of techniques have been developed in, the signal level is no longer compatible for it (all signals are differential modified) in place, has reached speeds up to 16Gbps. This 16Gbps data transfer speed to the stable (12 photo) is a major feature of XDR2 that, initially, such as replacement of GDDR5 graphics (or rather successor) seem to be targeting positions. 


[11] Although those photos XDR2 central controller, the two chips to its right (in emulation of silicon DRAM) XDR memory I / F 12 respectively shall be integrated 16Gbps right in photo] BER ( Bit Error Rate) shows the values, but actual write to show a steep decline curve is somewhat generally be required for BER 10 Eye Width at ^ -20 (10 ^ 20bit per send with 1bit errors. 16Gbps when it is actually carried out and continued to communicate with 1bit 198 years that there is an error level) is about ensuring that the 
Another was the introduction of Mobile XDR. This is the successor to LPDDR2 is aimed at replacing, but generally the same as the previous content (photo 13), we were shown the actual data and test silicon (14 photos) slightly different points s part.Has been shown to be much better energy efficiency (15 pictures) is also a difference between the previous. 


[13] In this picture, and specifically the small number of pins PoP (Package on Package) / MCP (Multi Chip Package) / C2C/Stack such appeal that the package used to implement support for mobile phones [14] In the picture outlined here, but only this year (2010) DesignCon that little information has been published in 2010.According to the Silicon controller test here is manufactured on TSMC's 40nm LP process, C2C PoP and a good eye diagram is recorded in both packages.DesignCon presentation in the package as LPDDR2 conduct also use was also shown that the disorder is much eye-diagram [15 photos] SerDes that the MIPI I / F (SPMT in is likely not) point to If you. Dr. Woo was later confirmed, this graph I / F is likely that both power consumption along with the memory chip itself. In short, multimedia data because of intense interaction, a much larger power consumption required for this communication, it seems that 
Interview with Dr. ● Steven Woo 
The following is an interview with Dr. Steven Woo. By the way, as well as an interview with Mr. Ashmore, who also attended the Strategic Marketing Manager, Rambus shed righteous, which he said includes some cabin. 

Q: In order to reduce the increase in power consumption, high I / O must be said that coming up at the GPU. GDDR1 → GDDR3 or indeed, GDDR3 → GDDR5 You talked in such. GPU does not now have much greater power than its earlier, I / O power consumption is a relatively large proportion do not feel that. 

A: It is an interesting story, as you know the GPU core and control logic for I / O PHY (physical layer) is composed. I / O PHY is but a very small area, power consumption is slightly larger. First I / O power consumption is proportional to the core logic technology as a process (to decrease) does not, there is a problem. Transistor logic (according to the refinement process) is reduced power consumption, I / O power transistors are to come down there. Therefore, the miniaturization process and will continue to, I / O power consumption would become more and more problems. GPU will continue to think about more and more bandwidth is required for such low-power I / O and I think the importance of high. 

Q: GPU when it comes, it GDDR but I think the main reason for the higher driving voltage of the memory. 

A: That's right, but of course, GDDR is a high voltage for a variety of other less susceptible to crosstalk and noise are some aspects that require high voltage. Room full of noise such as that, but do not talk loud and convey it lowers his voice even if you do not convey a quiet room. So What Single Ended Signaling problem. Unless you fix this, I / O voltage is not lower (and more power would remain.) Because we are a differential signal, the signal voltage can be lowered more. 

Q: Mobile XDR is about, certainly XDR Mobile at the moment would be one good solution. However, less mobile, so more power is much easier Daisutakkingu.Currently companies for this purpose to study the stacking and TSV used, circa 2013 time frame, 3D TSV currently using LPDDR2 LPDDR3 and successor may come out.What do you think of these? Mean, as you know now DDR4 JEDEC standards, but is conducted, there is a problem that is hard on the memory density, and the package vendors are using 3D TSV Memorichippubenda Kono Tame currently engaged in developing and increasing the memory density in the direction from which can be used as it is, but I mean that. 

A: The answer is, just how popular or widely applicable technology, will depend. This is the future of the CPU or memory chip, or to cover a wide range of platforms, how much involved as well. As well as conventional package, PoP and MCP, and stacking, which correspond to various packages, which of course can not help 跳Ne返Razaru price. Of course, Some applications of 3D TSV will I use to think. The problem is how much many of these 3D TSV applications that require, or will be widely used and how much it. Once that time frame, of course, I think such a solution would be to support us. In short, the (3D TSV's) who will bear the cost of platform development, or targeted towards the application of which is. This is also the problem of TSV and platforms as well as its own die. 

Of course, the future is going that direction, but I think it's about what it is exactly when I do not know. Just old, BGA remember when I stood up packages. Out more information about the reliability of vendors, to challenge the implementation of the packaging, and became increasingly popular. TSV 3D is something close to it.Currently there are no see still little information about reliability. 

This is a personal opinion, the first system vendor to 3D TSV will be able to get enough information about its reliability, I think it should refrain from the implementation. So, what is the actual implementation would be much later than 2012. Of course, if five years - 6 (3D TSV's) technology is not going to stand up for me. 

In addition to speaking, the state of the economy is still not so good, we want to do a vendor to launch a new infrastructure investment will not think too much. XDR Mobile perspective I think such a good choice. It is available directly from the existing infrastructure. This is also true of DDR4. As you know, was delayed because DDR4, DDR3 comes into play faster. It can be used without the existing infrastructure. I think this is true even in the same mobile. 

Q: Apple's iPhone for example, processors are manufactured by Samsung is not, Samsung is good for peripherals and memory controller IP and processor as well as stocks, so Apple does not own a separate memory controller was designed Samsung just simply select the memory controller has to offer. Like this Mobile XDR to be broadly accepted, simply Rambus is Mobile XDR soft IP not only provides that the foundry Mobile XDR physical IP requires a system that can provide will do no What? especially now, I feel this is a very important process is shrinking. For example Fab ARM is working with other GLOBALFOUNDRIES, 28nm physical IP for the following offers. 22nm or 28nm, so the initial cost is a huge development in the physical needs of IP is not really high. These foundries are also at the same time, a standard IP LPDDR2 physical IP that does not also justified the use of this inexpensive and reliable way. Mobile XDR Rambus But if the software purchased from IP, I'll have to implement it; do not own the customer? 

A: It is said as true. While development costs is higher. Knowledge is required, 28nm or less for the more rapidly it will be more expensive. Of course, these things are understood, we have an industry proven Mobile XDR physical measures to get software for IP and IP are planning to offer. 

Q: mobile, but does not mean that the SPMT is targeting the same market, what do you think their solution? 

A: In fact, fewer pins than in terms of higher data rates in the same direction, but I think as a total solution for the Mobile XDR is more better. Start with the idea of course, but we have such a memory I / F has accumulated 20 years of experience and enough knowledge about the past. XDR Mobile so asymmetric system, DRAM side just DRAM, and the necessary circuitry is integrated into the controller (note: SPMT has a parallel mode and serial mode, operating in parallel mode almost LPDDR2 but together with In serial mode to become a unique transfer system, DRAM also have to deal with this side.) It is also easy to test system for the motherboard, which also includes on-chip measurement circuit. Response to signal integrity and besides, various solutions have already been established in Mobile XDR. Mobile XDR Why do I think is better, other solutions are even speaking the same philosophy with the approach, the equivalent of 20 years of experience-based knowledge we're not.Mobile XDR think that this is the solution to correct. 

In addition to speaking, XDR Mobile is compatible with low pin count and low latency I / F is also a. 

Q: The application will remove it from a little mobile, for example, like the GPU is too much latency is not an issue, I have a problem or even bus width Masu Yoshi instead.

A: You're right about pure graphics. But recent cases such as the CPU and GPU work together to perform operations is a different story. If the graphics memory is not used as a frame buffer, in these cases a bandwidth problem. However, for example, Intel's Larrabee, AMD's Fusion, or if a different architecture that is also a latency problem.So I said that it is an important element of both bandwidth and latency. 10 Intel years ago, we proposed the concept of shielding the latency in high bandwidth environments (Note: It works by blocking the latency that is multi-threaded), which has been widely used, GPGPU story, but also changed I think coming. 

Besides, without latency, buffer size in the chip (or how much you have) or, if the depth of the pipeline or come in a variety of factors related to the others. So "if the latency to do?" If you listen to "as low as possible for me to" answer that comes back.GPU market still is a market that latency-sensitive than the bandwidth currently GPGPU will come as popular, but I think the latency comes increasingly important over time. 

Q: Then it is back to talk to GPU. The current generation of GPU GDDR5 256bit memory bus, but the configuration of some products, but NVIDIA has 384bit memory bus configuration. Probably would not technically a 512bit impossible. We will ask, in each generation will catch up in the GDDR, XDR and XDR2 do you think is needed? 

A: Technically speaking, the GPU is now prepared to die in a huge lot of pins. XDR2 is used, but it can greatly reduce the number of pins in the same band. So even a die shrink, I / O bandwidth is not necessary to sacrifice. Of course, if the chip giant may need XDR. If the compact chip size with the refinement process, but when it becomes effective solutions XDR. 

Q: It is not that right, but for now does not die is solely determined by the number of shaders, I / O pins, but this effect I think not many. 

A: This is I think the balance between cost and performance issues. If the pin can be achieved with less power consumption if the same band for example, the processor cores minutes (Note: shader in this case) increases. So the question becomes an issue of power and cost. The low pin count enables a smaller package, lower power consumption and heat dissipation mechanism leads to lower costs of on-board voltage regulator. So the problem with better performance will be called GDDR which are important for backward compatibility. Interestingly, GPU is a memory technology that has supported more in the past. We XDR2 the GPU to think that the best solution.

Q: Is this example (10 photos), but I think maybe Radeon or something in 3000, most of the die is not a shader, GDDR3 and GDDR5 transistors greatly reduced the XDR2 not changed just because And they have it? Also, here is why there are eight GDDR chip, the chip package itself is not much different XDR2 but I think it becomes. 

A: In short pins, GDDR5 170-pin, 150 pin against XDR2 will. However, the bandwidth per pin is more than doubled. So if you want even better performance if you can handle the XDR2, GDDR5 is impossible in a single-ended. And the wiring is very tough. 

Q: GPU and one around, PCB respect. If the recent high-end GPU, PCB levels have reached a considerable number of layers. Certainly since 2005 the 12-layer NVIDIA, ATI is said there were 14 layers, more than it should have. 12 and 14 layers of only 2005, but production is also very expensive and difficult, is not so today. 

This composition is similar to the PC market. When first debuted in 1999 Direct RDRAM, a four-tier motherboard vendors most of which could not manufactured by PCB, 6 PCB layers were used. Then, around 2000, technology vendors have now somehow be able to produce four layers. The now four-tier vendors are inexpensive and almost all the PCB rather 1GHz signals can now handle more than normal. This technology is widespread, it came up from the level of the whole. 

I think the same can be said with the video card, the 2005 256bit or wide signaling was very difficult, now is not so strange. When it comes to, XDR2 without using GDDR think I can make an inexpensive system based. 

A: The discussion can be understood. Compared to the previous PCB layers was certainly a major impact on prices so 及Bosanaku. We XDR2 4 16Gbps layer, but can not, it is difficult to be a big advantage on price. The problem is becoming a power supply rather than scaling and performance. But as long as GDDR is using an increasing number of PCB layers, if the number of layers you 減Rashitakere XDR2 is a good solution. 

Q: That is a problem, low-cost PCB + GDDR expensive or low-cost, high-priced XDR2 PCB + or - would be like that. 

A: Eventually a total cost problem. However it is also the question of how much volume comes out. If the shipping costs will be down a lot. 

Q: Here is the very question. DDR2 DDR3 is now completely gone compared to the price premium, while the next few years will come down in price rapidly. The GDDR5 Mosou premium has now gone. XDR is to say, however, are only now in mass production Elpida. In addition to the course that Samsung has licensed and I know them and hear "I want to produce it if customers", customers enter the desired volume unless other words So, Masu Hashi そうなると prices remain high. This is a typical "chicken and egg" not a state, how you intend to overcome this. 

A: This is true indeed. Our application for the "right" that wants to break this by introducing the solution. Our current staff, XDR2 doing and respond to just focus on applications that require capabilities. Maybe next year will be able to talk a little in this direction. Not only that, but would also be necessary to meet the needs of the system in other respects. For early adopters, we've done well in response to demands for technical aspirations are not only technical. The volume will want to ensure that it can help a lot more shipments of these early adopters. 

Q: What was true in 2007 or 2008 had, TI has adopted XDR controller DLP, Toshiba also has STB Solution for the XDR memory and adopted, adoption for consumers in other cases there You Do U? 

A: empowers customers to get more interested. XDR2 is a high-performance needs, and expected him to become the first cases of graphics and game consoles. XDR is already entering the market at a very large shipments. We just said, "any design or XDR or XDR2 best" is always thinking. The possibilities are very wide. 4-layer PCB of course, but also ideal for motherboards. 

Q: How about a little different way. Rambus is a non-standard XDR/XDR2 DDR/DDR2/DDR3 I / F of IP is also available. In, DDR3 I / F is said that FlexPhase contains technology has heard before. Other features So, what can we also include on-chip measurement capability has been in the earlier example? 

A: The on-chip features such as measurement was possible to combine all our products. PHY DDR3 is why we have a real chip measurement capability, FlexPhase are also features and others. None of these things that were created in the development of XDR. 

Earlier, DDR4 DDR3 because there is talk of extending that efforts were made to speed. Here we can use bond wires, 1,866 MHz DDR3 PHY available until last week.2,133 MHz operation and eye diagram is good too. These features and PHY on-chip measurement FlexPhase are equipped with both. 

Q: The DDR3 PHY is now 1.5V. 1.25V or 1.35V is just now expected to be standardized operation, support these standards would invite future. 

A: We are always going to support industry standards, are complicated to gather information. These businesses are also actively carried out, in the past HTDV in the market that last year when the market such as HDTV 20 percent of our PHY is employed. 

Q: DDR4 not you like? But I think that probably in 2015 or later. 

A: It is hanging on whether the customer demand. 

Q: Another feature on-chip measurement. This alone will be sold to as IP? 

A: I can. Separate each IP has been configured as a block, which can be incorporated into the design of the actual customer. 

Q: XDR2 for Another. But I hope ATI NVIDIA for example, but if they thought and XDR2 GDDR5 instead to use. But their architecture is currently GDDR3 / design is based on the 5, memory access optimization techniques XDR2 I think you would get quite different. 


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Replies
Msg # Subject Author Recs Date Posted
560178 Re: Steven Woo asked about the future of XDR sab63090 8 11/8/2010 3:41:47 PM
560200 Re: Steven Woo asked about the future of XDR wmkjohiv 0 11/8/2010 5:21:05 PM
560201 Re: Steven Woo asked about the future of XDR // Sabatino..'mabree somtring get woss in twaswation' LOL Gotta love the translation. LTL_KAHUNA LTL_KAHUNA 1 11/8/2010 5:26:33 PM
560202 Re: Steven Woo asked about the future of XDR dfwl28 2 11/8/2010 5:37:53 PM






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