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United States Patent Application | 20110286280 |
Kind Code | A1 |
Kellam; Mark D. ; et al. | November 24, 2011 |
Pulse Control For NonVolatile Memory
AbstractThis disclosure provides a nonvolatile memory device that uses pulsed control and rest periods to mitigate the formation of defect precursors. A first embodiment uses pulsed bitline control, where the coupling between a memory cell channel and a reference voltage (selected in response to the bitline) is pulsed when it is desired to change state in the associated memory cell. Each pulse may be chosen to be less than about (20) nanoseconds, while a "rest period" between pulses typically is chosen to be on the order of about a hundred nanoseconds or greater (e.g., one microsecond). Because bitline control is used, very short rise times can be enabled, enabling generation of pulse durations of (50) nanoseconds or less. In other embodiments, these methods may also be more generally applied to other conductors (e.g., wordline or substrate well, for program or erase operations); if desired, segmented wordlines or bitlines may also be used, to minimize RC loading and enable sufficiently short rise times to make pulses robust.
Inventors: | Kellam; Mark D.; (Siler City, NC) ; Haukness; Brent Steven; (Monte Sereno, CA) ; Bronner; Gary B.; (Los Altos, CA) ; Donnelly; Kevin; (Los Altos, CA) |
Assignee: | RAMBUS INC. Sunnyvale CA |
BACKGROUND
[0001] Nonvolatile memory can retain stored information without the continual requirement of short-interval refresh operations, i.e., such that memory contents can be retained in the absence of external power for at least as long as typical on/off times of electronic devices; for these reasons, nonvolatile memory can save power, enable new applications and further extend functionality of portable devices. [0002] To date, one of the most cost-effective forms of nonvolatile memory is flash memory, which unfortunately suffers from use-based degradation. That is to say, flash memory in particular eventually loses its ability to retain information for any length of time, with current expected lifetime being about 10,000-100,000 read and write cycles. It is believed that one primary cause of this life cycle wear is damage to the oxide layers in these devices from the formation of traps that arise under the influence of high electromagnetic fields used in programming ("setting") and erasing ("resetting") of device memory cells. Although the physics associated with trap formation are not precisely understood, it is believed that these traps are the result of precursors, which form and develop over short periods of time to ultimately become permanent. Life cycle wear is a significant limitation for nonvolatile memory, and has generally inhibited application of flash memory in environments calling for high read and write turnover (e.g., main memory for portable computers). [0003] A need exists for ways of minimizing this damage, so as to extend the useful life of nonvolatile memory, reduce maintenance, and enable new applications. The present invention satisfies these needs and provides further, related advantages.>>